1. Technical Field
This invention relates in general to semiconductor packages and in particular to the integration of multiple, finished semiconductor components into a high density, single chip format.
2. Background Art
As described in U.S. Pat. No. 5,814,885, which is incorporated herein by reference, a precision alignment macro process is used to bond individual semiconductor chips or components together with an unfinished semiconductor package to form a single, larger, higher density integrated chip. The advantage of this process is that multiple chips can be placed very close together (within 50 microns of one another) so that the interconnect wiring distances are minimized. As discussed in the patent, the wiring or electrical connections between the components are made after they are joined together. Although this design is workable, it would be beneficial to eliminate the additional processing steps required to perform the interconnection between the components after they are joined.